Improving run times by pruned application of synthesis transforms

Abstract

In this paper, we describe methods to speed up integrated placement and synthesis of high performance designs. We present an analysis of the computation times of various logic synthesis transforms. We then show techniques to reduce computation time based upon judicious selection of gates and nets for the resizing and buffering transforms, respectively. We show that it is possible to obtain savings of up to 28% in CPU time without compromising the quality of the results. For large high performance designs that are quite common these days our savings could translate into several hours of CPU time. Copyright 2005 ACM.