Interfacial layer optimization of high-k/metal gate stacks for low temperature processing

Abstract

Understanding the requirements for obtaining high mobility gate stacks in a low temperature process is crucial for enabling a low temperature integration flow. A low temperature integration scheme may be necessary for higher-k dielectrics (k > 25) or for extremely scaled devices (<15 nm node). This paper demonstrates that nitrogen free interfaces are required for high mobility gate stacks in a low temperature (600 °C) process flow. © 2009 Elsevier B.V. All rights reserved.