Issues in CPU-coprocessor communication and synchronization

Abstract

This paper deals with the issues in microprocessor fixed and floating-point processors communication and synchronization. In a micro-system consisting of a Fixed Point processor, and Floating-Point coprocessor, it is essential that the two units work at their maximum utilization rate. Three different environments are examined in terms of number of chips. They can consist of each of the units being a separate chip, or two of the units, or all of them being integrated on a single chip. In terms of coupling of the two (or more) processor they can execute their instructions in a lockstep, or run as a complex of independent units. The synchronization strategies are examined in this paper and two approaches for achieving higher performance are proposed. © 1988.