Large Feature Wafer Level In-Line Optical Metrology Techniques for Advanced Packaging Schemes

Abstract

Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically sizes. Large-scale 3D structures needs to be characterized with unprecedented accuracy and advanced optical techniques play a pivotal role.​ In this paper, we introduce and discuss dimensional and overlay metrology challenges related to TSV integration schemes. Specific examples will be presented and capabilities as well as limitations discussed.