Layout Optimization at the pinnacle of Optical Lithography

Abstract

This paper attempts to shed more light on the widely acknowledged need to improve the manufacturability of integrated chip layouts for sub-100nm technology nodes. After reviewing the parametric performance targets and time constraints of the 65nm and 45nm technology nodes, the paper elaborates on the principles of popular resolution enhancement techniques, their impact on chip layouts, and the opportunity for broad layout improvement which they afford. Finally, the viability and feasibility of layout optimization based on a design-for-manufacturability mantra and enabled through 'radically design restrictions' is explored.