Low power design from moore to AI for nm era : Invited paper

Abstract

This paper reviews key developments and the continuation of low power techniques needed from the Moore to AI eras. SRAM with a wider range of operation, from extreme low to high voltages, is enabled using novel circuit techniques and demonstrated for edge or data centric accelerators. These techniques exploit interconnect as well as inductor and capacitor coupling for boosting on demand. Several chips fabricated in 14nm SOI technology show functional 8T SRAM down to 0.24V-0.30V These new techniques can lead to lower voltage operation of cognitive and neural network for IoT and data centric applications.