Abstract
How can the semiconductor industry improve the communication between what is done up front in the design, and what is done downstream in the fab and during test? This panel will examine whether product test can provide the necessary "grand unification" to solve today's broken handoffs between DFM, test chips, and fab yield management systems. Questions addressed include: What does the "grand unification" look like? Who are the key stakeholders and their roles in this unification? What new value, benefit and ROI will stakeholders realize from their roles? What is the "gap" of technologies and data flows that need to be deployed to make this work? In what order and when will we see these appear? And what are the limiters to this vision?