Memory system prefetching for multi-core and multi-threading architecture

Abstract

A helper thread active prefetching technology was proposed to make the prefetching thread in the helper core run ahead the main thread in the main core. The helper thread attempted to trigger future cache miss events in advance of accessing by the main thread to avoid the memory missing latency. As a special prefetching mechanism, compared with the traditional helper thread method, the problem of resource confliction between the main thread and the helper thread was solved. The simulation results showed that this new prefetching method could improve Instruction per Cycle (IPC) by 11.3% and could improve the long latency loads hitting in cache ratio by 101.3%, over no helper thread prefetching policy. Based on improved trigger instruction selection, a pre-trigger helper thread active prefetching technology was proposed. The simulation results showed that this optimization policy could improve IPC by 14.5% and could improve the long latency loads hitting in cache ratio by 132.5% on average, over no helper thread prefetching policy. © 2010 IEEE.