Minimizing chip-level simultaneous switching noise for high-performance microprocessor design

Abstract

This paper describes the on-chip power bus modeling and switching noise analysis for high performance circuit design, and the methodology to minimize simultaneous switching noise by optimizing the placement of on-chip decoupling capacitors. The switching noise is analyzed at both the package level and the chip level. An equivalent circuit which consists of time-varying resistors, loading capacitors, and decoupling capacitors, is used to simulate the switching activities of functional blocks. Both the resistive and inductive voltage drops on the power bus are modelled to identify the hot spots on the chip and ΔV across the chip. Based on the noise analysis results, we can determine the amount of decoupling capacitance needed to keep the power supply voltage within specification, and optimize the final size and location of on-chip decoupling capacitors.