Netlisting and modeling well-proximity effects

Abstract

In advanced CMOS technologies, transistor characteristics depend not only on the layout of the device itself but also on the layout of the adjacent structures. For the compact model to accurately predict circuit behavior, it needs information about the transistor and the structures surrounding it. For the simulator to efficiently handle a large number of transistors, the information about the surrounding layout must be reduced to a small number of parameters for each transistor instance. The parameters must be such that they can be efficiently calculated from the layout by the layout-versus-schematic tool. This paper describes the solution chosen by the Government Electronics and Information Technology Association Compact Model Council for modeling the effect of well edges near a transistor and proposes general guidelines for efficient solutions for modeling other proximity layout effects. © 2006 IEEE.