Optimization of materials and interfaces for low power analog Conductive Metal Oxide/HfO2 ReRAM artificial synapses

Abstract

The energy required for the training and inference of complex neural networks on standard CMOS technology based on von-Neumann architecture has been growing tremendously. In particular, the data exchange between memory and the processing units is power-hungry, causing inefficiency and performance mitigation. Specialized neuromorphic hardware based on analog memristors are a promising and more energy efficient alternative. When organized in crossbar arrays, memristive technologies such as ReRAM or PCMs [1] can be used to perform vector-matrix multiplications (VMMs), the most energy-expensive operation in AI’s tasks, in the analog domain, by exploiting Ohm’s and Kirchhoff’s law. Such two-terminal technologies are scalable and can be densely integrated in the Back end of the line (BEOL) of existing CMOS technology, to create a high performing synaptic analog signal processing accelerator. Metal/Insulator/Metal Redox-based Resistive Switching Random Access Memories $ (Ti/HfO_{2}\space ReRAM) $, exploiting filamentary conduction, are emerging as a leading option for memristors due to the compatibility with and ease of integration in CMOS technology. Nonetheless, the electro-chemical reactions at the interface between Ti and $ HfO_{2} $ tend to result in an abrupt and stochastic rather than analog and symmetric switching characteristics, hindering their suitability for applications in AI analog accelerator units [1]. A promising and innovative concept of ReRAM device was proposed in [2], replacing the Ti layer by an engineered Conductive Metal Oxide (CMO), resulting in a Metal/CMO/Insulator/Metal type ReRAM device. The $ CMO/HfO_{2}\space ReRAM $shows superior characteristics such as gradual, linear and symmetric conductance update, large number of states, good retention and reproducibility of the switching characteristics. Nevertheless, the main limitation of $ CMO/HfO_{2} $ stack with respect to $ Ti/HfO_{2} $ is the increased voltage required to perform the electro-forming (Vfoming up to 5.5V in [2]), which represents a critical challenge for combining this technology with modern CMOS technology. In this work, we optimized the Metal/CMO/Insulator/Metal ReRAM technology. By properly engineering the stack, we reduced the forming voltage below 3.3V without compromising all the superior electrical characteristics of the CMO based ReRAM technology. The material-stack characterization by means of TEM and EDS, as well as the DC and pulsed electrical characterization of the devices will be presented. Furthermore, by controlling the forming process of $ CMO/HfO_{2}\space ReRAM $, two operative switching regimes are found, with kΩ and MΩ range resistive levels. Through impedance spectroscopy experiments and finite elements simulations, we established equivalent electrical circuit models and provided a physical understanding of the optimized $ CMO/HfO_{2}\space ReRAM in pristine state, after forming, in the high resistive state (HRS) and in low resistive state (LRS), explaining the importance of the CMO layer in the resistive switching behavior. The granular switching properties and CMOS compatibility of the CMO/ReRAM devices are promising for large-scale integration of this technology for future neural network training and inference. [1] Ielmini, D., Wong, HS.P. In-memory computing with resistive switching devices. Nat Electron 1, 333–343 (2018). https://doi.org/10.1038/s41928-018-0092-2 [2] T. Stecconi, et al. (2022). Filamentary TaOx/HfO2 ReRAM Devices for Neural Networks Training with Analog In‐Memory Computing. Advanced Electronic Materials. 8. 10.1002/aelm.202200448.