Performance of large low-associativity caches

Abstract

While it is known that lowering the associativity of caches degrades cache performance, little is understood about the degree of this effect or how to lessen the effect, especially in very large caches. Most existing works on cache performance are simulation or emulation based and there is a lack of analytical models characterizing performance in terms of different configuration parameters such as line size, cache size, associativity and workload specific parameters. We develop analytical models to study performance of large cache architectures by capturing the dependence of miss ratio on associativity and other configuration parameters. While high associativity may decrease cache misses, for very large caches the corresponding increase in hardware cost and power may be significant. We use our models as well as simulation to study different proposals for reducing misses in low associativity caches, specifically, address space randomization and victim caches. Our analysis provides specific detail on the impact of these proposals, and a clearer understanding of why they do or do not work.