Power-conscious design of the cell processor's synergistic processor element

Abstract

The authors describe the low-power design of the synergistic processor element (spe) of the cell processor developed by Sony, Toshiba and IBM. CMOS static gates implement most of the logic, and dynamic circuits are used in critical areas. Tight coupling of the instruction set architecture, microarchitecture, and physical implementation achieves a compact, power-efficient design. © 2005 IEEE.