Power-supply considerations for future scaled CMOS systems

Abstract

The relationship between operating voltage, speed, and power consumption is examined for future proposed submicron (approximately 0.5 μm) and deep submicron (0.25 μm) CMOS technologies for logic and static RAM applications. The scaling of DRAM (dynamic RAM) operating voltages to low levels is discussed. The practical problems associated with low-voltage power-supply regulation and distribution, either centrally in the system or on each chip, are considered. Interfacing chips with different voltage levels is also discussed.