Power supply noise induced jitter estimation in high speed clock tree for full chip timing analysis

Abstract

As semiconductor technology advances, low supply voltage and high performance requirements make the clock jitter more critical to the integrated circuit (IC) design. In this paper, a 32nm test vehicle is built to characterize and analyze on-chip power supply noise. Clock jitter sensitivity to noise frequency and amplitude is investigated. By studying noise characteristics and jitter sensitivity to noise, a cell based jitter model generation method is introduced. This enables clock tree jitter calculation and flexible "what if' analysis with reduced run time, which is the key for STA early on in the design phase. The estimation result on a real design is studied and shows good correlation to conventional jitter analysis method.