Queue machines for next generation computer systems

Abstract

Queue processors are a novel computer architecture with characteristics that are suitable for the next generation computer systems. Compared to conventional register machines where registers referenced by their names are used for data processing, the queue machines use a nameless first-in first-out queue to perform operations. The head of the queue is the only place where data is read and the tail of the queue is the only place where data can be written. Thus, queue computing allows instructions to read and write data without using register names and, as a consequence, instructions are short and the queue programs are free of false dependencies. Small instructions are preferred over longer instructions since memory traffic can be reduced, the cache performance and size can be improved, and decoding hardware logic can be simplified. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. In this paper we present the special characteristics of queue machines that make such design a very suitable architecture for the future generation of computer systems demanding high-performance, low power, and low cost. We present the toolchain of compilers, translators, assembler, virtual machine, functional and cycle accurate simulators, and RTL processors we have designed and developed. From our experimental results we demonstrate that queue programs are smaller than conventional register programs and have very similar characteristics in terms of parallelism.