Reliable memories with subline accesses

Abstract

We study memories protected with error control codes, in which the memory's contents are organized in lines which are read and written to in isolation from other lines. In these memories the available redundancy is structured so as to protect individual lines rather than the entire memory as a whole. Often designers wish to read and write only parts of the memory line, as in some instances this leads to various favorable system design tradeoffs, including better power consumption, increased data access concurrency, etc. (alternatively one may say that designers sometimes would prefer smaller line sizes). Nevertheless when designing systems with such subline accesses it is often found that in order to mantain a given level of reliability, the total amount of redundancy allocated in the memory needs to be increased beyond desirable levels. In this work, we initiate a study of the problem of structuring error control codes to allow subline accesses with good tradeoffs between reliability and redundancy. We motivate and explore a setting in which a "double-lookup" protocol is used in conjunction with certain types of two-level codes, whereby error detection is attained in a first level and error correction using the second level is performed whenever errors are detected in the first level. We obtain lower bounds on redundancy for a given level of reliability and offer a code construction that attains this bound for a certain important class of parameters. We also introduce an alternate construction which allows us to find longer codes under restrictions of the Galois Field size used in the codes. ©2007 IEEE.