Role of high aspect-ratio thin-film metal deposition in Cu back-end-of-line technology

Abstract

The transition in manufacturing from Al(Cu)/W to Cu multilevel on-chip line/via ULSI wiring for high-performance CMOS logic chips was initiated in late 1997 and has since become the exclusive industry-standard. The authors provide a comprehensive review of metal thin-film deposition methods and techniques as they apply to the ULSI of Cu interconnects in advanced logic technology. The authors discuss the basic features of Cu dual-damascene processing with a focus on physical vapor deposition and atomic layer deposition techniques, which have enabled the continued scaling of Cu interconnects over many generations of technology. In addition, the authors discuss recent experimental and simulation data on the extendibility of Cu interconnects to future technology nodes.