Scalable PD/SOI CMOS with floating bodies

Abstract

An insightful analysis of the floating-body (FB) effect on off-state current (I off) in PD/SOI MOSFET's is done based on simulations calibrated to a published scaled SOI CMOS technology [1]. In contrast to the conclusion drawn in [1], the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I off, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.