Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

Abstract

Using a novel replacement gate SOI FinFET device structure, we have fabricated FinFETs with fin width (DFin) of 4nm, fin pitch (FP) of 40nm, and gate length (LG) of 20nm. With this structure, we have achieved arrays of thousands of fins for DFin down to 4nm with robust yield and structural integrity. We observe performance degradation, increased variability, and VT shift as DFin is reduced. Capacitance measurements agree with quantum confinement behavior which has been predicted to pose a fundamental limit to scaling FinFETs below 10nm LG. © 2011 JSAP (Japan Society of Applied Physi.