Sub-30 nm abrupt P⁺ junction formation with Ge preamorphization and high energy Si co-implantation

Abstract

Experiments have been carried out to form ultra-shallow (Xj<50 nm) and abrupt (Xjs<5 nm/decade) P+ junction for sub-50 nm CMOS devices using a combination of shallow implant, Ge preamorphization and high energy Si implant as an interstitial getter layer. Experimentally, it was observed that the Si getter layer, not only stopped the TED at the boron tail but also promoted enhanced diffusion close to the surface boron peak. These unique features have enabled the shallowest and sharpest box-like boron junction yet achieved by implant. With 1 kV BF2, Xj to approximately 23 nm, Xjs to approximately 48 A/decade, no Ge end of range damages and good dopant activation at the same time. The sheet resistance ρ to approximately 1 kohm/sq is comparable to shallow BF2+Ge and is better than the shallow BF2 alone (ρ to approximately 2.38 kΩ/sq) or the shallow BF2+Si implants (ρ to approximately 1.5 kohm/sq). Tests with device leakage test structures show that there is no additional junction leakage introduced by the Si getter layer.