Tacue: A timing-aware cuts enumeration algorithm for parallel synthesis

Abstract

Achieving timing-closure has become one of the hardest tasks in logic synthesis due to the required stringent timing con-straints in very large circuit designs. In this paper, we pro-pose a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: (1) a new divide-and-conquer strategy is proposed that generates mul-tiple sub-cuts on the critical parts of the circuit; (2) two cut enumeration strategies are proposed; (3) an effcient parallel synthesis framework is offered to reduce computation time. Experiments on large and diffcult industrial benchmarks show the promise of the proposed method. Copyright 2014 ACM.