Technology trends in sub-0.5 μm bipolar

Abstract

The technology trends in scaling silicon bipolar towards sub-0.5 μm dimensions are projected by examining the delay components in the power-delay characteristics of bipolar logic circuits. The directions for technology developments include (i) further reduction of the parasitics of the trench-isolated 'double-poly' self-aligned device structure, including the use of dielectric-filled deep trenches, shallow trenches, and emitter-trench butting, (ii) further optimization of the vertical device profile, including reduction of the emitter junction depth, and (iii) emphasis on minimizing the base-push-out effect by optimizing the collector doping profile while maintaining adequate E-C punch-through voltage. The new and exciting opportunities offered by heterojunction structures, epitaxy base, high-performance pnp, and low-temperature circuit operation are also discussed.