The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si tunnel FETs

Abstract

The effect of traps in the hetero-junction and at the oxide interface on slope and ON-current of vertical and lateral InAs/Si Nanowire (NW) Tunnel FETs (TFETs) is demonstrated through physics-based TCAD analyses in combination with experimental findings. The high density of interface states (Dit) at the highly lattice-mismatched material interface degrades the sub-threshold swing (SS) and makes band-to-band tunneling (BTBT) completely dominated by Shockley-Read-Hall (SRH) generation and trap-assisted tunneling (TAT) up to high gate voltages. When the NW diameter is scaled into the volume-inversion regime, the TFET can even turn into an artificial MOSFET with close-to-60mV/dec slope due to the intrinsic Si channel. The only remedy is then given by a "trap-tolerant" geometry where the gate edge is aligned with the hetero-junction.