The theory of signature testing for VLSI

Abstract

Several methods for testing VLSI chips can be classified as signature methods. Both conventional and signature testing methods apply a number of test patterns to the inputs of the circuit. The difference is that a conventional method examines each output, while a signature method first accumulates the outputs in some data compression device, then examines the signature - the final contents of the accumulator -to see if it agrees with the signature produced by a good chip. Signature testing methods have several advantages, but they run the risk that masking may occur. Masking is said to occur if a faulty chip and a good chip behave differently on the test patterns, but the signatures are identical. When masking occurs, the signature testing method will incorrectly conclude that the chip is good, whereas a conventional method would discover that the chip is defective. This paper gives theoretical justification to the use of several signature testing techniques. We show that for these methods, the probability that masking will occur is small. An important difference between this and other work is that our results require very few assumptions about the behavior of faulty chips. They hold even in the presence of so-called correlated errors or even if the circuit were subject to sabatoge. When we speak of the probability of masking, we use the probabilistic approach of Gill, Rabin and others. That is, we introduce randomness into the testing method in a way which can be controlled by the designer. Thus, one theorem assumes that the order of the input patterns - or the patterns themselves - is random; another assumes that the connections between the chip and the signature accumulator are made randomly, and a third assumes that the signature accumulator itself incorporates a random choice. Most of the results of this paper use a particularly simple and practical signature accumulator based on a linear feedback shift register.