Thermal performance evaluation of dual-side cooling for a three-dimensional (3D) chip stack: Additional cooling from the laminate (substrate) side

Abstract

When a 3D chip stack is composed of some memories and a logic device such as processor, the logic device has been assumed to be located as a bottom chip in wide I/O and HBM applications. On the other hand, for high-end server applications, a processor needs to be located as a top chip because it needs to be cooled efficiently. In this case, many Through Silicon Vias (TSVs) are necessary in a memory (bottom chip), because a processor (top chip) requires many electrical connections (power, ground, signal) with a substrate [1]. However, when effective cooling from the bottom side of chips ( from the substrate side) is achieved, a processor can be located as a bottom chip, and only a small numbers of TSVs are required in a processor which electrically connects a memory and a substrate [2,3].