Thermal power plane enabling dual-side electrical interconnects for high-performance chip stacks: Implementation

Abstract

We report on the design, implementation and performance of a laminate named Thermal Power Plane and solder joints that enable dual-side electrical interconnects (EIC) to a chip stack. This novel packaging topology with a laminate on both sides of the chip stack doubles the number of EIC thus supporting increased communication bandwidth and power density. In addition, in a two-die stack, all power TSVs can be eliminated with the advantage of gained silicon active area. The use of two laminates also enables individual test & burn-in of the dies before stack formation. The TPP needs to provide efficient heat removal and current feed in the out-of-plane and in-plane direction, respectively. An 8+1 coreless build-up laminate with aligned and stacked thermal laminate vias (TLVs) was designed and implemented. Bar-, chevron- and mesh-like copper planes with varying TLV densities were characterized. The mesh design resulted in minimal warpage and voltage drop. The bar and chevron designs result in the lowest thermal resistance. In combination with rail-shaped solder interconnects interfacing between TPP and top chip, the overall thermal resistance of the junction to cold plate of the dual-side EIC approach can outperform that of the standard single-side EIC package. The electrical DC characteristics of the TPP was also evaluated experimentally. The sheet resistance of 0.21 MΩ allows the supply of the required currents within the voltage uniformity requirements. In general, the experimental evaluation supports the feasibility of the proposed dual-side EIC concept supporting further performance and efficiency scaling of highperformance chip stacks.