Time stamp invalidation of TLB-unified cache and its performance evaluation

Abstract

This article proposes the TLB-unified cache, which is one of the indirect tagged cache implementation methods. In the indirect tagged cache, the cache tag functions as a pointer to another address. It requires less hardware than the conventional method. In order to maintain the consistency between the indirect tag and the cache in the indirect tagged cache, however, there must be a high-speed selective cache invalidating mechanism. From such a viewpoint, this article proposes time stamp invalidation as one of the invalidating mechanisms. We present an implementation of time stamp invalidation for the TLB-unified cache, where the TLB and the cache share a tag. As the next step, the amount of hardware resources that can be saved by using the indirect tag is evaluated. It is then shown that the saved hardware resources can be transferred to other on-chip units in order to improve their performance. Lastly, the performance of the TLB-unified cache is evaluated by trace-driven simulation, and it is shown that the performance can be improved with less hardware complexity than the conventional method.