Timing derived current for signal net reliability assessment

Abstract

In this paper, we present a practical CAD methodology for very large scale integrated (VLSI) circuits designer to perform signal net electromigration and Joule-heating analysis. Electromigration is normally considered to be a design concern only in power grids but not in signal nets due to the sweep back effect of bidirectional current. However, unidirectional current exist in some part of signal net. The self heating of a wire, where bidirectional current dominates, will make its neighboring wires more vulnerable to electromigration problems because of the sensitivity to temperature. Thus, during the design of a high performance microprocessor, we developed this timing-based signal net reliability assessment tool as part of a full chip integrity check. We present the result and some observations from application of this methodology on a test micro.