Understanding of enhanced sensitivity to Hot Carrier degradation in drain engineered n-FETs

Abstract

Various drain engineering techniques have been proposed for submicron CMOS devices to reduce high electric field. In this paper, we demonstrate that the enhanced device degradation due to Hot-Carrier (HC) is very sensitive to the drain doping profile near gate-to-drain overlap region. The enhanced device degradation, decrease of channel current and increase of Gate-Induced Drain Leakage (GIDL), is found to be more significant in Lightly Doped Drain (LDD) than in abrupt junction and Fully Overlap Lightly Doped (FOLD) drain devices. The enhanced device degradation in LDD devices is shown to be due to the fact that the HC damages locate outside the gate-to-drain overlap region where damage-induced barrier cannot be suppressed by the applied gate voltage. The significant increase of Band-To-Band (B-T-B) tunneling currents observed in LDD devices is shown to be caused by the fact that the HC damage is located at where the maximum field for B-T-B tunneling current occurs.