Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

Abstract

A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Young's modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.