Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor

Abstract

Present-day circuit-analysis tools permit designers to verify performance for circuits consisting of up to 10 000 transistors. However, current designs often exceed several tens of thousands and even hundreds of thousands of transistors. The gap between the number of transistors that can be simulated and the number per design inhibits proper analysis prior to manufacturing, yet incomplete analysis often overlooks design flaws and forces redesign, resulting in increased costs and longer development times. This gap is expected to widen in the foreseeable future. To help close the ever-increasing simulation/design gap, we have developed an experimental parallel circuit simulator, WRV256, for the Victor V256 distributed-memory parallel processor. WRV256 has been used to analyze circuits from fewer than 300 to more than 180 000 MOSFETs. WRV256 was originally based on a Gauss-Seidel relaxation algorithm, which was later replaced with a bounded-chaotic one in order to achieve good parallel speedups for a wider variety of circuits. At this time, speedups of up to 190 have been observed for large circuits.