Publications

This is our catalog of publications authored by IBM researchers, in collaboration with the global research community. It’s an ever-growing body of work that shows why IBM is one of the most important contributors to modern computing.

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21 results for Hazar Yueksel

A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- - Danny Luu
  - Lukas Kull
  - et al.
- 2017
- VLSI Circuits 2017
Design considerations on sliding-block viterbi detectors for high-speed data transmission
- - Hazar Yueksel
  - Giovanni Cherubini
  - et al.
- 2016
- ICSPCS 2016
High-speed link with trellis-coded modulation and Reed-Solomon coding
- - Hazar Yueksel
  - Giovanni Cherubini
  - et al.
- 2016
- CSCN 2016
CMOS ADCs Towards 100 GS/s and beyond
- - Lukas Kull
  - Danny Luu
  - et al.
- 2016
- CSICS 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- - Hazar Yueksel
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- - Thomas Toifl
  - Matthias Braendli
  - et al.
- 2016
- ESSCIRC 2016
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- - Hazar Yueksel
  - Lukas Kull
  - et al.
- 2015
- ESSCIRC 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- - Alessandro Cevrero
  - Cosimo Aprile
  - et al.
- 2015
- VLSI Circuits 2015
A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI
- - Marcel Kossel
  - Christian Menolfi
  - et al.
- 2014
- ESSCIRC 2014
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- ESSCIRC 2014