Towards production ready processing with a state-of-the-art EUV clusterKaren PetrilloNicole Saulnieret al.2015SPIE Advanced Lithography 2015
EUV processing and characterization for BEOLNicole SaulnierYongan Xuet al.2015SPIE Advanced Lithography 2015
Characterization and mitigation of overlay error on silicon wafers with nonuniform stressT.A. BrunnerV. Menonet al.2014SPIE Advanced Lithography 2014
CD optimization methodology for extending optical lithographyC. WongG. Seevaratnamet al.2013SPIE Advanced Lithography 2013
Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stressTimothy A. BrunnerVinayan C. Menonet al.2013Journal of Micro/Nanolithography, MEMS, and MOEMS
High order wafer alignment in manufacturingMichael PikeNelson Felixet al.2012SPIE Advanced Lithography 2012
Advanced overlay control in volume manufacturingTimothy WiltshireChristopher Ausschnittet al.2011ASMC 2011
Overlay improvement roadmap: Strategies for scanner control and product disposition for 5-nm overlayNelson M. FelixAllen H. Gaboret al.2011SPIE Advanced Lithography 2011
Smaller, smarter, faster, and more accurate: The new overlay metrologyNelson M. FelixAllen H. Gaboret al.2010SPIE Advanced Lithography 2010
Simultaneous measurement of optical properties and geometry of resist using multiple scatterometry gratingsAlok VaidMatthew Sendelbachet al.2010SPIE Advanced Lithography 2010
IBM and Albany partners unlock new yield benchmarks for EUV patterningTechnical noteLuciana Meli and Nelson Felix24 Oct 2024Semiconductors
EUV patterning yield breakthrough sets new benchmark for logic scalingTechnical noteNelson Felix and Luciana Meli06 Nov 20204 minute readAI HardwareHardware TechnologyLogic ScalingSemiconductors
IBM Research at SPIE 2020: New architectures and fabrications for AI hardwareResearchNelson Felix21 Feb 20204 minute readAI HardwareSemiconductors
MBMary BretonTechnical Assistant to Huiming Bu | Semiconductor Enablement Program Management & Infrastructure