A Low-Capacitance Bipolar/BiCMOS Isolation Technology, Part I—Concept, Fabrication Process, and Characterization

Abstract

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to ⋍30%, the collector-base capacitance to ⋍70%, and the extrinsic base contact resistance to >50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology. © 1994 IEEE.