A low-power mm wave CML prescaler in 65nm SOI CMOS technology

Abstract

A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.4fJ power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time. © 2008 IEEE.