Advanced plasma etch for the 10nm node and beyond

Abstract

As 14nm node devices begin to permeate into the semiconductor industry, it is becoming increasingly evident that continued pitch scaling is getting more complex throughout the FEOL, MOL and BEOL. The adoption of patterning schemes and pitch splitting techniques such as double exposure/double etch and sidewall image transfer (SIT) are already underway to extend 193nm immersion lithography and enable 3D FinFET / Trigate devices. In addition, BEOL scaling of damascene copper is facing its own challenges, between the patterning and integration of porous ULK materials and the issue of increased resistivity emanating from grain boundary and surface scattering. As such, this paper will present work on novel etch methods envisioned to enable the successful extension of patterning and device integration for the 10nm node and beyond. Work related to the exploration of novel feedgas chemistries to extend etch performance for SiN spacer and oxide etch applications will be reviewed in detail. Specifically, the realization of a silicon nitride etch process which no longer depends on an oxidation mechanism, but rather a polymerization based etch mechanism will be shown. The process exhibits high selectivity to SiO2, Si and photoresist and results in reduced SOI loss while simultaneously maintaining all SiN on the gate sidewall and significantly reducing SiN footing. In addition, the feasibility of novel patterning methods such as the introduction of subtractive etching of copper will be reviewed in detail. Subtractive etching of Cu has the potential to overcome current interconnect integration difficulties by enabling blanket Cu film deposition with large grains, and by minimizing plasma damage during ULK etch, respectively. Successful patterning of copper at 25-50nm critical dimension (CD) with smaller than 100nm in pitch is demonstrated using a novel high density plasma based dry etch process. © 2013 SPIE.