Capacitance investigation of diode and GGNMOS for ESD protection of high frequency circuits in 45nm SOI CMOS technologies

Abstract

S-parameter test structures from a 45nm SOI CMOS technology show total capacitance per perimeter of poly-bounded ESD diodes ranges from ~0.35-0.42fF/μm, and silicide-block (SBLK) bounded diodes show ~15-20% capacitance reduction. Floating-body or notched-silicon tied-body Gate-Silicided GGNMOS devices show total capacitance per width of ~0.65fF/um for thin oxide devices, and ~0.72fF/μm for thick oxide devices.Gate-Non-Silicided devices have ~20% higher capacitance because of increased junction area. © 2008 ESDA.