Dynamic trace analysis for analytic modeling of superscalar performance

Abstract

The advent of superscalar processors introduces additional architectural design tradeoffs. Identifying the potential performance impact of these tradeoffs early is critical in achieving a high performance/cost ratio. To study performance, a method of analyzing dynamic instruction traces to characterize program parallelism is introduced. This technique allows performance evaluation of many architectural variations with a single execution pass through an application or benchmark of interest. A new parameter, the β α ratio, is used to quantify the available parallelism within programs versus the scope of concurrency detection. Performance is evaluated within a framework of multi-instruction issue, speculative execution, dynamic scheduling, and finite scope of concurrency detection. A trace-driven superscalar simulator was developed to extend the validation of a previously developed analytic model to dynamic trace analysis. Using actual execution traces from four science/engineering application benchmarks, the throughput prediction of the model is shown to be close to the throughput measured via the simulator. © 1994.