Impact of process monitoring in semiconductor manufacturing

Abstract

Short cycle time in manufacturing leads to not only fast problem recognition and verification of solutions, reduction in partially finished product inventories and the final product costs, but most importantly, it provides a key vehicle for early market entry of the technology products. In contrast, deep-submicron CMOS usually involves processes with high complexity and tight process tolerance. By necessity, this dictates frequent process monitoring with send ahead test wafers in order to assure accelerated yield learning during early phases of manufacturing. However these send ahead test wafers, although beneficial in the overall yield improvement, will increase the total raw (theoretical) process time and decrease the equipment availabilities for real processing in the line. In this paper, we examine the impact of send ahead test wafers on process cycle time, wafer throughput, and fab line equipment capacity requirements. Discrete Event Simulation was used to run a hypothetical fab model with an industry standard CMOS base process. Examples will be given for fab sizes ranging from early manufacturing 50 wafer starts per day to high volume 600 wafer starts per day. We will demonstrate that with careful planning in equipment capacity ramping in early manufacturing phases, send ahead process monitoring can be practiced without lengthening the cycle time, decreasing the line throughput, and placing any additional burdens in the total cost of capital investment in the fab line.