Modeling of gate-induced drain leakage mechanisms in silicon-germanium channel pFET

Abstract

Silicon-Germanium is used as an alternative channel material for pFET in high-k metal gate-first technologies for 32 nm and beyond. However, gate-induced drain leakage (GIDL) is significant at nominal bias due to band-to-band tunneling (BTBT) at the gate-to-drain overlap surface and gate sidewall junctions. In this work, the results of numerical simulation are compared with experimental results for SiGe channel pFET and the calibrated models are used to describe the GIDL mechanisms in the dominant region for various drain and gate bias voltages. The simulation results correspond well with the experimental data, illustrating that the models presented in this paper can be used to describe the GIDL mechanisms and help to reduce the overall leakage budget for low-leakage, high-threshold voltage (HVT) device designs.