USE OF TiSi//2 FOR SELF ALIGNED SILICIDE (SALICIDE) TECHNOLOGY.

Abstract

In VLSI technology, as the devices continually scale to submicron dimensions, the line resistance and the series resistance of FETs which includes the contact resistance and the diffusion sheet resistance become a limiting factor. The strategy of siliciding both the polysilicon gate and single-crystal silicon diffusion areas for contacts and interconnects appears to be a logical and attractive solution to this problem. The self-aligned silicide process (salicide) appears to be the best approach. TiSi//2 is perhaps the most promising candidate because of the consistent silicide formation, thermal stability, low resistivity, and, most important, absence of bridging across the gate and the diffusion areas. The device structure and process flow using TiSi//2 for this application are described. A few critical issues tied closely to the success of this technology such as the elimination of bridging across gate and diffusion, the interaction between Ti and SiO//2 and the high temperature limitation on TiSi//2 are reviewed.