A NRZ/PAM4 SST TX in 5nm FinFET CMOS with 3-tap FFE and 0.7pJ/b efficiency at 100 Gb/s PAM4
- 2024
- ESSERC 2024
Marcel Kossel
Title
Circuit Designer
Bio
Education:
- 1997: MSEE ETHZ
- 2000: PhD EE ETHZ
- 2001: NDS EE ETHZ
Job Title: Senior Research Scientist, 2022
Memberships: IEEE Senior Member, 2009
Research Activities: Integrated Circuit Design (analog, mixed-signal)
Research Areas:
- Wireline communication, high-speed interconnect technology
- High-speed data converters and equalizers
- Hardware implementation of neural networks
- Control electronics for quantum computing
Papers: 90+ (status 2024)
Patents: 50+ (status 2024)
Publications
A 40 GS/s 8b-DAC SST-TX in 7 nm FinFET CMOS for cryogenic quantum applications with 32kB SRAM-based RF-DDS AWG
- 2024
- ESSERC 2024
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-based Wireline Transceivers
- Donggeon Kim
- Yujin Choi
- et al.
- 2024
- IEEE TCAS-I
A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- ISCAS 2024
A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation On RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration
- Tod Dickson
- Zeynep Toprak Deniz
- et al.
- 2024
- CICC 2024
A DAC/ADC-based Wireline Transceiver Datapath Functional Verification on RFSoC Platform
- Jaewon Lee
- Seoyoung Jang
- et al.
- 2024
- IEEE TCAS-II
Design of synchronous frequency dividers in 5-nm FinFET CMOS technology
- 2023
- Electronics Letters
Patents
- US
- 12095473
- US
- 12088316
- US
- 12088314
- TW
- I851057
- TW
- I850965
- US
- 11916568
- US
- 11816062
- US
- 11811418
- US
- 11652493
- CN
- ZL201880035590.8
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
PF
Pier Andrea Francese
Principal RSM - Analog Circuit Design
MB
Matthias Brändli
Digital Circuit Design
TM
Thomas Morf
Senior Research Scientist
CZ
Cezar Zota
Staff Research Scientist, Master inventor