A 24-to-72GS/s 8b time-interleaved SAR ADC with 2.0-to-3.3pJ/conversion and >30dB SNDR at nyquist in 14nm CMOS FinFET
- Lukas Kull
- Danny Luu
- et al.
- 2018
- ISSCC 2018
Bio
Pier Andrea Francese received the Laurea degree in electrical engineering (cum laude) from the Politecnico di Milano, Italy, and the Ph.D. degree from the Federal Institute of Technology of Zurich (ETH), Switzerland, in 1993 and 2005, respectively. He is currently a Principal Research Staff Member at the IBM Zurich Research Laboratory in Rueschlikon, Switzerland, and he serves as the Technical Leader of the high-speed interconnect technology group. His research interests are in the areas of high-speed data converters, analog equalization and clock-data-recovery circuit techniques for wireline and optical transceivers and, more recently, in analog signal processing for in-memory and quantum computing.
Publications
A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS
- Christian Menoifi
- Matthias Braendli
- et al.
- 2018
- ISSCC 2018
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS
- Ilter Ozkaya
- Alessandro Cevrero
- et al.
- 2018
- ISSCC 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels
- Cosimo Aprile
- Alessandro Cevrero
- et al.
- 2018
- IEEE JSSC
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
- Ilter Ozkaya
- Alessandro Cevrero
- et al.
- 2017
- IEEE JSSC
DDR4 transmitter with ac-boost equalization and wide-band voltage regulators for thin-oxide protection in 14-nm SOI CMOS Technology
- Marcel Kossel
- Christian Menolfi
- et al.
- 2017
- ESSCIRC 2017
Background calibration using noisy reference ADC for a 12b 600MS/s 2×TI SAR ADC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- ESSCIRC 2017
VCSEL-based optical links in burst-mode slow optical power ramp-up and how to achieve ultra-short wake-up times
- Thomas Morf
- Marc Seifried
- et al.
- 2017
- Electronics Letters
A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- VLSI Circuits 2017
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- Elisa Sacco
- Pier Andrea Francese
- et al.
- 2017
- VLSI Circuits 2017
Patents
- US
- 12095473
- US
- 12088316
- DE
- 11 2019 000 181
- TW
- I850965
- GB
- 2620314
- KR
- 2672586
- CN
- ZL201980010119.8
- SG
- 11202110345X
- US
- 11916568
- JP
- 7427030
Projects
High-Speed I/O Links
Designing the next generation High-Speed I/O Links targeting low power consumption, low latency and small silicon area.
Top collaborators
MB
Matthias Brändli
Digital Circuit Design
TM
Thomas Morf
Senior Research Scientist
MK
Marcel Kossel
Circuit Designer
VC
Victor Chan
Yield learning & Diag Eng Prof