Matthias Brändli

Publications

• CMOS ADCs Towards 100 GS/s and beyond

  • • Lukas Kull
    • Danny Luu
    • et al.
  • 2016
  • CSICS 2016

• Feedback delay reduction of Tomlinson- Harashima precoder in 14 nm CMOS via pipelined MAC units operated entirely with CSA arithmetic

  • • Marcel Kossel
    • Matthias Braendli
    • et al.
  • 2016
  • Electronics Letters

• A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS

  • • Hazar Yueksel
    • Matthias Braendli
    • et al.
  • 2016
  • ESSCIRC 2016

• Design considerations for 50G+ backplane links

  • • Thomas Toifl
    • Matthias Braendli
    • et al.
  • 2016
  • ESSCIRC 2016

• Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

  • • Lukas Kull
    • J. Pliva
    • et al.
  • 2016
  • IEEE JSSC

• A 30Gb/s 0.8pJ/b 14nm FinFET receiver data-path

  • • Pier Andrea Francese
    • Matthias Braendli
    • et al.
  • 2016
  • ISSCC 2016

• A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS

  • • Hazar Yueksel
    • Lukas Kull
    • et al.
  • 2015
  • ESSCIRC 2015

• A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

  • • Alessandro Cevrero
    • Cosimo Aprile
    • et al.
  • 2015
  • VLSI Circuits 2015

• A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm² in 32 nm SOI CMOS

  • • Lukas Kull
    • J. Pliva
    • et al.
  • 2014
  • A-SSCC 2014

• A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth

  • • Pier Andrea Francese
    • Thomas Toifl
    • et al.
  • 2014
  • IEEE JSSC